Printed circuit boards include discrete components, which are interconnected with copper (or other conductive) traces that are photolithographically applied to the board on which the components are mounted. The traces on the printed circuit board can be laid out manually, or if more complex, multi-level boards are involved, may be routed using a computer. Analogously, large ICs, which include hundreds or thousands of components that must be interconnected using conductive traces applied to an underlying substrate are normally far too complex to be routed manually. The conductive traces are usually defined in at least two layers, including vertical traces in one layer and horizontal traces in another, which can be electrically connected at designated points using vias that extend between the layers. To define a conductive path between two points on the substrate, a computer routing program is normally employed. The program selects portions of the vertical and horizontal conductive traces that will most efficiently (i.e., using the shortest route) provide the required interconnection without interfering with or short circuiting other interconnections that have already been assigned. As necessary, the program lays out "jogged" or "dogleg" paths to accomplish this goal.
Interconnection of ICs in a multichip module presents a new level of difficulty. A multichip module is a substrate on which the ICs are attached by wire bonding or tape automated bonding (TAB) techniques. By attaching a plurality of ICs to a common substrate in this manner, higher system performance, lower weight, and smaller size can be achieved than is possible with traditional printed circuit boards on which discrete ICs are mounted. Since the number of interconnections often is in the thousands, manual routing of conductive interconnections is virtually impossible. Traditional computer assisted circuit board routing techniques would use the area under the ICs for laying out connection paths; however, in multichip modules, the ICs must be mounted directly onto the substrate to insure good thermal conductivity and the underlying area is not available to form layers in which conductive traces can be formed. Thus, the ICs are mounted in spaced apart array directly onto the substrate, and only part of the areas between the ICs are typically used for routing channels.
Input and output terminals on the boundaries of each IC comprising a multichip module are connected by very thin wires to conductive pads using the wire bonding or tape automated bonding operations. The pads are generally aligned with and spaced apart from each side of the ICs. In routing interconnections between these pads on a multichip module according to prior art methods, only the areas between the pads of adjacent ICs have been used for routing channels; the areas between the boundaries of each IC and its associated pads (each such area comprising a strip at least 50 mils wide) have not been used for interconnection of the pads and have thus been wasted. Commonly assigned U.S. patent application Ser. No. 314,817, filed Feb. 22, 1989 describes the use of these previously wasted areas, referred to as side channels, for interconnecting pads. Ideally, the conventional (central) routing channel, which comprises only the area between the pads of adjacent ICs, should be as narrow as possible to allow the maximum number of chips to be mounted on a given size substrate. Conventional routing methods are not equipped to handle routing of interconnects through the side channels and can only be used if the area between the pads and the IC boundaries can be wasted, i.e., where the density of ICs mounted on the multichip module is not an important concern.
Accordingly, it is an object of the present invention to provide a method for interconnecting a plurality of ICs in a multichip module so as to maximize chip density on the module. It is a further object of the invention to preferentially interconnect pads on a multichip module using side routing channels that are disposed between the boundaries of the ICs mounted on a substrate and pads to which the ICs are electrically connected. A still further object is to minimize the width of a central routing channel defined between the pads of adjacent ICs comprising a multichip module. These and other objects and advantages of the present invention will be apparent from the attached drawings and from the Description of the Preferred Embodiments that follows.